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Security Level: Confidential A - 12 - 2/27/2018
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
ORDERING GUIDE
Part Number Temperature Range Package Description Package Option
SSD102 -40°C to +85°C LQFP 100-pin
MARKING INFORMATION
SSD102
DISCLAIMER
SIGMASTAR TECHNOLOGY RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE
TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. NO
RESPONSIBILITY IS ASSUMED BY SIGMASTAR TECHNOLOGY ARISING OUT OF THE APPLICATION
OR USER OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY
LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Electrostatic charges accumulate on both test equipment and human body and can discharge without
detection. SSD102 comes with ESD protection circuitry; however, the device may be permanently
damaged when subjected to high energy discharges. The device should be handled with proper ESD
precautions to prevent malfunction and performance degradation.
Sigmastar Confidential for
芯智国际有限公司
Internal Use Only
Security Level: Confidential A
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
REGISTER DESCRIPTION
General Control Register
General Control Register
Index Name Bits Description
00h
REGBK 7:0 Default : 0x00 Access : R/W
XTAL_OK (RO) 7 Crystal ready.
MCU_SEL (RO) 6 0: Embedded MCU.
1: External serial bus interface.
- 5:4 Reserved.
AINC 3 Serial bus address auto Increase.
0: Enable.
1: Disable.
- 2 Reserved.
REGBK[1:0] 1:0 Register Bank Select.
00: Register of scaler.
01: Register of ADC/ACE/MCU.
10: Register of Video Decoder Front End (VFE).
11: Register of Video Decoder 2D Comb Filter (VCF).
REGBK[2:0] 2:0 Register Bank Select.
000: Register of scaler.
001: Register of ADC/ACE/MCU.
010: Register of Video Decoder Front End (VFE).
011: Register of Video Decoder 2D Comb Filter (VCF)
01h ~
FFh
- 7:0 Default : - Access : -
- 7:0 Reserved.
Scaler Register (Bank = 00, Registers 01h ~ 9Fh)
Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
01h
DBFC 7:0 Default : 0x80 Access : R/W
- 7:3 Reserved.
DBL[1:0] 2:1 Double Buffer Load.
00: Keep old register value.
01: Load new data (auto reset to 00 when load finish).
10: Automatically load data at VSYNC blanking.
11: Reserved.
Sigmastar Confidential for
芯智国际有限公司
Internal Use Only
Security Level: Confidential A
Copyright © 2018 SigmaStar Technology Corp. All rights reserved.
Scaler Register (Bank=00, Registers 01h ~ 9Fh)
Index Name Bits Description
DB_EN 0 Double Buffer Enable.
0: Disable.
1: Enable.
02h ISELECT 7:0 Default : 0x00 Access : R/W
NIS 7 No Input Source.
0: Input source active.
1: Input source inactive, output is free-run.
STYPE[1:0] 6:5 Input Sync Type.
00: Auto detected.
01: Input is separated HSYNC and VSYNC.
10: Input is Composite sync.
11: Input is sync-on-green (SOG).
COMP 4 CSYNC/SOG select (only useful when STYPE = 00).
0: CSYNC.
1: SOG.
ICS 3 Input Color Space.
0: RGB.
1: YCbCr.
IHSU 2 Input Sync Usage.
When EXTVD=0:
0: Use HSYNC to perform mode detection, HSOUT from ADC to
sample pixel.
1: Use HSYNC only.
When EXTVD=1:
0: Normal.
1: Output black at blanking.
BYPASSMD 1 By-Pass Mode for interlace-input-interlace-output.
EXTVD 0 0: Select analog input (CVBS/S-Video/RGB/YCbCr).
1: Select digital input (CCIR656).
03h IPCTRL2 7:0 Default : 0x18 Access : R/W
VDS_EN 7 Input data double sample
In CCIR input mode,
0: for horizontal output resolution less than 720 pixels.
1: for horizontal output resolution more than 720 pixels.
In analog input mode,
0: half sample of input data.
1: original sample of input data.

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